[31] Manuel Le Gallo, Abu Sebastian,Giovanni Cherubini, Heiner Giefers, Evangelos Eleftheriou. Compressed Sensing With Approximate Message Passing Using In-Memory Computing. IEEE Transactions on Electron Devices 65 (10), 2018
[30] Manuel Le Gallo, Abu Sebastian, Roland Mathis, Matteo Manica, Heiner Giefers, Tomas Tuma, Costas Bekas, Alessandro Curioni, Evangelos Eleftheriou. Mixed-precision in-memory computing. Nature Electronics 1 (4), 2018
[29] Heiner Giefers, Dionysios Diamantopoul. Extending the POWER Architecture with Transprecision Co-Processors. Int. Symp. on Circuits and Systems (ISCAS), 2018
[28] Dionysios Diamantopoulos, Heiner Giefers, Christoph Hagleitner. ecTALK: Energy efficient coherent transprecision accelerators – The bidirectional long short-term memory neural network case. IEEE Symp. in Low-Power and High-Speed Chips (COOL CHIPS), 2018
[27] Raphael Polig, Kubilay Atasu, Heiner Giefers, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, Peter Hofstee. A Hardware Compilation Framework for Text Analytics Queries. Journal of Parallel and Distributed Computing, 111: 260-272, Elsevier, 2018
[26] Manuel Le Gallo, Abu Sebastian, Giovanni Cherubini, Heiner Giefers, Evangelos Eleftheriou. Compressed Sensing Recovery using Computational Memory. IEEE Int. Electron Devices Meeting (IEDM), 2017
[25] Heiner Giefers, Peter Staar, Raphael Polig. Energy-Efficient Stochastic Matrix Function Estimator for Graph Analytics on FPGA. Field Programmable Logic and Applications (FPL), 2016 (Best Paper Award Nominierung)
[24] Peter W. J. Staar, Panagiotis Kl. Barkoutsos, Roxana Istrate, A. Cristiano I. Malossi, Ivano Tavernelli, Nikolaj Moll, Heiner Giefers, Christoph Hagleitner, Costas Bekas, Alessandro Curioni. Stochastic Matrix-Function Estimators: Scalable Big-Data Kernels with High Performance. Parallel and Distributed Processing Symposium (IPDPS), 2016 (Best Paper Award)
[23] Heiner Giefers, Peter Staar, Costas Bekas, Christoph Hagleitner. Analyzing the Energy-Efficiency of Sparse Matrix Multiplication on Heterogeneous Systems: A Comparative Study of GPU, Xeon Phi and FPGA. Int. Symp. on Performance Analysis of Systems and Software (ISPASS), 2016
[22] G. Georgakoudis, C. Gillan, A. Hassan, U. Minhas, G. Tzenakis, I. Spence, H. Vandierendonck, R. Woods, D.S. Nikolopoulos, M. Shyamsundar, P. Barber, M. Russell, A. Bilas, S. Kaloutsakis, H. Giefers, P. Staar, C. Bekas, N. Horlock, R. Faloon, C. Pattison. NanoStreams: Codesigned Microservers for Edge Analytics in Real Time. Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016
[21] Christoph M. Angerer, Raphael Polig, Djordje Zegarac, Heiner Giefers, Christoph Hagleitner, Costas Bekas, Alessandro Curioni. Fast, Hybrid, Power-Efficient High-Precision Solver for Large Linear Systems based on Low-Precision Hardware. Sustainable Computing: Informatics and Systems, Elsevier, 2015
[20] Heiner Giefers. Enabling Energy-Efficient Exascale Computing: Acceleration of HPC Kernels with Reconfigurable Hardware. Platform for Advanced Scientific Computing Conference (PASC), 2015
[19] Heiner Giefers, Raphael Polig, Christoph Hagleitner. Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT. Journal of Signal Processing Systems}, Springer, 2015
[18] Raphael Polig, Heiner Giefers, Walter Stechele. A soft-core processor array for relational operators. Proc IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP), 2015
[17] Heiner Giefers, Raphael Polig, Christoph Hagleitner. Accelerating Arithmetic Kernels with Coherent Attached FPGA Coprocessors. Proc. Design, Automation, and Test in Europe Conference and Exhibition (DATE), 2015
[16] Raphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu. Compiling text analytics queries to FPGAs. Int. Conf. on Field Programmable Logic and Applications (FPL'14), 2014
[15] Jan van Lunteren, Heiner Giefers, Christoph Hagleitner, Rik Jongerius. Memory-Driven Near-Data Acceleration. HPC User Forum, 2014
[14] An FPGA-based Reconfigurable Mesh Many-Core. IEEE Transactions on Computers, 63(12): 2919-2932, 2014
[13] Heiner Giefers, Christian Plessl, Jens Förstner. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News, 41(5): 65-70, Jun. 2014
[12] Heiner Giefers, Raphael Polig, Christoph Hagleitner. Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system. Proc IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP), 2014 (Best Paper Award Nominierung)
[11] Heiner Giefers, Christian Plessl, Jens Förstner. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. Proc. Int. Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2013
[10] Heiner Giefers. Design and Programming of Reconfigurable Mesh based Many-Cores. Dissertation, Logos Verlag, Berlin, 2012
[9] Heiner Giefers, Marco Platzner. A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. Int. Conf. on Field Programmable Logic and Applications (FPL), 2010 (Best Paper Award Nominierung)
[8] Heiner Giefers, Marco Platzner. A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010
[7] Heiner Giefers, Marco Platzner. Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009
[6] Heiner Giefers, Marco Platzner. Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. Int. Conf. on Architecture of Computing Systems (ARCS), 2009
[5] Heiner Giefers, Marco Platzner. ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. Reconfigurable Architectures Workshop (RAW), 2009
[4] Heiner Giefers. Reconfigurable Many-Cores with Lean Interconnect. Int. Conf. on Field Programmable Logic and Applications (FPL), 2008
[3] Heiner Giefers, Marco Platzner. Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. Int. Symp. on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2008
[2] Heiner Giefers, Marco Platzner. A Many-Core Implementation Based on the Reconfigurable Mesh Model. Int. Conf. on Field Programmable Logic and Applications (FPL), 2007
[1] Heiner Giefers, Achim Rettberg. Energy Aware Multiple Clock Domain Scheduling for a Bit-serial, Self-timed Architecture. Symp. on Integrated Circuits and Systems Design (SBCCI), 2006
Patente
[9] Dionysios Diamantopoulos, Heiner Giefers, Christoph Hagleitner. ARTIFICIAL NEURAL NETWORK IMPLEMENTATION IN FIELD-PROGRAMMABLE GATE ARRAYS. US Patent Application US 2020/0257986 A1, 2020
[8] Heiner Giefers, Raphael Polig, Jan van Lunteren. BIT-SERIAL LINEAR ALGEBRA PROCESSOR. US Patent US20190377707A1, 2019
[7] Costas Bekas, Alessandro Curioni, Heiner Giefers, Christoph Hagleitner, Raphael C. Polig, Peter W. J. Staar. SPARSE MATRIX MULTIPLICATION USING A SINGLE FIELD PROGRAMMABLE GATE ARRAY MODULE. US Patent US9558156B1, 2017
[6] Christoph M Angerer, Konstantinos Bekas, Alessandro Curioni, Heiner Giefers, Christoph Hagleitner, Yves G. Ineichen, Raphael C Polig. LINEAR FE SYSTEM SOLVER WITH DYNAMIC MULTI-GRID PRECISION, US Patent US20170024356A1, 2017
[5] Heiner Giefers, Raphael Polig , Jan Van Lunteren. INDEX BASED MEMORY ACCESS. US Patent US20180074962A1, 2016
[4] Heiner Giefers, Raphael Polig. INTERPOSER FOR DYNAMIC MAPPING OF API CALLS. US Patent US9703573B1, 2016
[3] Christoph M Angerer, Heiner Giefers, Raphael Polig. DIFFERENTIAL DATA ACCESS. US Patent 20160170652A1, 2016
[2] Jan Van Lunteren, Heiner Giefers. MEMORY AND PROCESSOR HIERARCHY TO IMPROVE POWER EFFICIENCY. US Patent 20160077577, 2016
[1] Christoph M Angerer, Konstantinos Bekas, Alessandro Curioni, Silvio Dragone, Heiner Giefers, Christoph Hagleitner, Raphael C Polig. ITERATIVE REFINEMENT APPARATUS US Patent 20150234783, 2015
